Technical Field
The present disclosure relates to integrated circuits, and more particularly, to integrated circuit structures having a thin gate dielectric device and a thick gate dielectric device, and a method of forming the same.
Related Art
In integrated circuit (IC) structures, a transistor is a critical component for implementing digital circuitry designs. Generally, a transistor includes three electrical terminals: a source, a drain, and a gate. By applying different voltages to the gate terminal, the flow of electric current from the source to the drain can be turned on and off. A common type of transistor is a metal oxide field effect transistor (MOSFET). One type of MOSFET structure is a “FINFET,” typically formed upon a semiconductor-on-insulator (SOI) layer and buried insulator layer. A FINFET can include a semiconductor structure etched into a “fin” shaped body, with one side of the fin acting as a source terminal and the other side of the fin acting as a drain terminal. A gate structure, typically composed of polysilicon and/or a metal, can be formed around one or more of the semiconductor fins. The gate structure may typically include a gate dielectric and a gate conductor. In a FINFET, the gate dielectric may separate the gate conductor and the semiconductor fins. The gate dielectric may include, for example, an oxide. The gate conductor may include one or more conductive materials or layers including work function metal layers which effectively tune the work function of the gate structure. By applying a voltage to the gate structure, an electrically conductive channel can be created between the source and drain terminals of each fin in contact with the gate.
More than one gate structure (multi-gate or dual-gate) can be used to more effectively control the channel. Multi-gate FETs are considered to be promising candidates to scale down FET technology. However, the smaller dimensions associated with multi-gate FETs (as compared to single-gate FETs) necessitate greater control over performance issues such as short channel effects, punch-through, metal-oxide semiconductor (MOS) leakage current, and the parasitic resistance that is present in a multi-gate FET.
In a multi-gate FET, both a thin gate dielectric device and a thick gate dielectric device may be formed on the same semiconductor substrate. Thick and thin gate dielectric devices are so named due to the relative thickness of the gate dielectrics used in creating the gate structures for the FET devices. That is, in a multi-gate FINFET, one gate structure may have a thin gate dielectric separating the gate structure from the semiconductor fins thereunder, and another gate structure may have a thick gate dielectric separating the gate structure from the semiconductor fins thereunder. A thin gate dielectric may be used for a high performance logic transistor and may conventionally operate at about 0.9 volts (V), and a thick gate dielectric may be used for a high voltage input/output transistor used for analog, mixed signals, embedded Dynamic Random Access Memory (eDRAM) pass-gate, and system on chip applications, and may conventionally operate between about 1.5 V to about 3.0 V.
In manufacturing a FINFET having both types of gate dielectrics, i.e., a thin gate dielectric and a thick gate dielectric, an initial oxide is formed over the semiconductor fins. An oxide hard mask is generally formed on the top of the initial oxide over the semiconductor fin in the region which is to subsequently include the thick oxide device. The oxide hard mask protects the oxide over the semiconductor fin in the thick gate dielectric device region while thin gate dielectric device region undergoes additional processing, e.g., the removal of the initial oxide from over the semiconductor fin in the thin gate dielectric device region. While the oxide hard mask sufficiently protects the thick oxide device region during the processing of the thin oxide device region, the oxide hard mask must eventually be removed from the thick oxide device region in order to create the gate structure and complete the FINFET. Conventionally, during the deposition and removal of the oxide hard mask from the thick oxide device region, the initial oxide over the semiconductor fin in the thick oxide device region is reduced by about 2 Angstroms to about 3 Angstroms in thickness. That is, the deposition of the sacrificial oxide and subsequent removal of the same compromises the quality of the gate dielectric that needs to be retained and can lead to device and parametric shift from ideal characteristics desired.